A semiconductor apparatus used for a high speed data processing apparatus etc. is designed so that the semiconductor elements are highly integrated and obtain large power for increasing the data processing speed. As a result, the thermal capacity generated at the semiconductor elements exceeds a limit value by which cooling may be effected by means of forced air cooling. Accordingly, it is proposed that such semiconductor elements are cooled by water, etc. of liquid or a boiling cooling medium in a semiconductor apparatus used for a large scale computer, etc..
As one method of cooling effectively a number of semiconductor elements mounted on a wiring substrate using a cooling liquid such as water, etc., there is an individual cooling method which cools semiconductor elements, respectively. For instance, such an individual cooling method is disclosed in FIG. 2 of Japanese Patent-Laid Open No. 60-160151 published on Aug. 21, 1985 with the title of "Cooling Method of Integrated Circuit", and FIG. 10 of Japanese Patent-Laid Open No. 61-220359 published on Sept. 30, 1986 with the title of "Cooling Structure of Semiconductor Module".
These known individual cooling methods for the semiconductor elements are characterized that a cooling plate is mounted on a semiconductor element, a bellows is connected between a housing having a channel of cooling liquid and the cooling plate, and a cooling liquid flowing through the housing is contacted by the cooling plate so that the semiconductor element is cooled, as will be explained later referring to FIGS. 1 and 2.
According to these individual cooling methods, the cooling effect of the semiconductor elements can be enhanced and the thermal resistances of the semiconductor elements can be decreased, since the cooling liquid can be introduced near the semiconductor elements.
Referring to FIG. 1, which corresponds to FIG. 2 of Japanese Patent-Laid Open No. 60-160151, 49 denotes a thermal conductive grease, 51 leads, 52 bonding wires, 53 a chip carrier (package), 54 solder connecting portion, 6 a cooling plate, 30 a O ring, 31 an flange, and 44 a nozzle. In the structure shown in FIG. 1, a thermal transmitting channel becomes short since cooling water is conducted near a LSI chip 9, and the cooling ability can be enhanced largely as compared with the conventional cooling method which cools the LSI chip by thermal conduction of a cooling fin since the device shown in FIG. 1 has not a space on a route of the thermal conducting channel. Since the displacements along the perpendicular and horizontal directions can be absorbed by the operation of the bellows 2 and the thermal conductive grease 49 against the thermal strain caused by the temperature difference or the thermal expansion coefficients between the wiring substrate 12 and the housing 1, a thermal fatigue service life can be enhanced at the solder connecting portion which is located between the package and the wiring substrate.
On the other hand, the device disclosed in FIG. 1 uses grease whose thermal conductivity is worse more than one figure compared with a metal for the purpose of having variable formation at stress of zero to the thermal conducting channel from the LSI chip to the cooling water. And, it is difficult to reduce the thickness of the grease to lower than ten .mu.m on account of the surface tension of the grease. Therefore, it is difficult to decrease the cooling ability lower than 1.degree. C./Watt of the thermal resistance. Accordingly, when a LSI chip is used in future, whose heating value exceeds more than 40 watts per one chip, the prior cooling structure of the device can not cope with the demanded cooling ability.
Referring to FIG. 2, which corresponds to FIG. 10 of Japanese Patent-Laid Open No. 61-220359, 61 and 62 denote solder connecting portions having a low melting point. In the structure shown in FIG. 2, since the distance between the cooling water and the LSI chip 9 is shorter than that shown in FIG. 1, and the thermal conducting channel is made of a metal or ceramic having a suitable thermal conductivity, the cooling performance of the device shown in FIG. 2 is remarkably improved compared with that shown in FIG. 1 so that the thermal resistance thereof becomes lower than 0.5.degree. C./Watt. However, in the device shown in FIG. 2, since all the elements from the cooling plate 6 comprising the cap 3 and the cooling fin 4 to the wiring substrate 12, which is connected to the LSI chip 9 via the solder 10, are fixed by solders, the bellows 2 has to absorb all the thermal strains between the housing 1 and the wiring substrate 12. Although the displacement is absorbed by the deformation of the bellows when a thermal stress is produced between the wiring substrate and the housing, the stress is applied directly to the soldered connecting portions between the wiring substrate and the semiconductor elements.
In general, a bellows is easily deformed along the axial direction, but is not easily deformed to the vertical direction against the axial direction. Accordingly, large stress is produced by the displacement along the horizontal direction of the wiring substrate and the housing. On the contrary, the fatigue service life of the soldered connecting portion between the wiring substrate and the semiconductor elements is small under the compression stress, but is remarkably decreased under the shearing stress, namely the above-mentioned stress to the horizontal direction.
Accordingly, when the wiring substrate is made larger than 10 mm, the fatigue service life of the soldered connecting portion between the wiring substrate and the semiconductor elements is decreased based on the thermal stress in the shearing direction caused by the thermal variation in assembling or using the semiconductor module made by the solder connection so that the reliability of the device is remarkably reduced.